The invention relates to distributed clock circuits and more particularly to a method and circuit of detecting synchronizing edges in a PLL system.
Demands created by high-speed electronic equipment have generated a number of problems for circuit designers and manufacturers. For example, many applications require that two subsystems running at different frequencies communicate with each other. Generally, logic running at a given clock frequency is said to be operating in a clock domain.
This synchronization problem has been previously addressed either by a single clock system architecture, which eliminates the number of clock domains, or by a multiple clock system architecture, which adds synchronization logic. Although utilizing a single clock system is simple, straightforward and low cost, each subsystem in the single clock system may not be optimized to its fullest potential, downgrading overall system performance. Also, there are practical limitations as to how many components a single clock source may support. Thus, a single clock system is not always feasible in most situations.
Alternatively, in multiple clock system architecture, dual ports or/and two port memories are required to transform blocks of information between different clock domains. This enables each subsystem to be optimized to its fullest potential, providing a robust solution. However, the dual port or/and tow port memories produce additional hardware cost. Additionally, the synchronization logic between different clock domains causes synchronization delay and meta-stability problems, adding latency. The disparity between the clock domains often includes different frequencies and/or phases, complicating the synchronization circuit design and adding significantly to the latency cost.
U.S. application Ser. No. 6,836,521 discloses a distributed clock generator loop based on gear ratio and phase alignment techniques to address the synchronizing problem while minimizing any latency caused by the additional synchronization circuitry. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles in a common period. Also, in addition to a gear ratio relationship, the clocks may have a synchronized edge at the end of the common period to be phase aligned. For each clock, the cycles in the common period are “colored”, i.e., identified by a number (1st, 2nd, etc.). Using the coloring technique, the appropriate clock edge for a data or control signal transfer can be identified. The edges are preferably chosen to minimize latency of the transfer. The distributed clock generator loop enables each subsystem to be optimized to its fullest potential, providing a robust solution at lower costs than a multiple clock system.
FIG. 1 shows clock waveforms of an exemplary gear ratio wherein three cycles of clock CLK1 10 equal two cycles of clock CLK2 20, or 3* (cycle of CLK1)=2* (cycle of CLK2). As shown, CLK1 and CLK2 are phase aligned at the end of the common period. Since gear ratio is defined as the ratio of the two clock frequencies, in this example the gear ratio of CLK1/CLK2 is 3/2. If clock signals CLK1 10 and CLK2 20 are divided by 6 and 4, respectively, a clock signal 30 results which is equal to CLK1/6 or CLK2/4.
FIG. 2 shows a distributed generator loop 200 applied to a Memory Control Unit 206 with two clock domains operating in gear ratio fashion disclosed in U.S. application. Ser. No. 6,836,521. The architecture contains a clock source 202, a distributed clock generator (DCG) 204, and Memory Control Unit 206 with logic running in two clock domains, PCLK 208 and SCLK 210. The clock source 202 generates PCLK 208 for Memory Control Unit 206 and a reference signal PEFCLK 240 for the distributed loop. DCG 204 receives PEFCLK 240. PEFCLK 240 is multiplied utilizing clock dividers, 212 and 214, and a phase-locked loop (PLL) 216 to generate LOOPCLK 218 of another frequency. The output of PLL 216 is a phase aligner 220. The output frequency of the phase aligner 220 is equal to its input frequency, but the output phase is delayed from the input phase by an error signal Err 238 output from a phase detector 222.
The phase detector compares the relative phases of PCLK_M 224 and SCLK_N 226 from a gear ratio Logic 228 in Memory Control Unit 206 and outputs the error signal Err 238 to drive the phase aligner 220 until the phase of SCLK_N 226 matches the phase of PCLK_M 224. When the output phase of the phase aligner 220 changes, the phase of SCLK 210 will have the same amount of phase change, and phase error between PCLK 208 and SCLK 210 is minimized.
FIG. 2 shows two sub-blocks 230 and 232 in gear ratio Logic 228. The sub-block 230 divides PCLK 208 by M to generate PCLK_M 224 and PCOLOR 234,; and the clock divider 232 divides SCLK 210 by N to generate SCLK_N 226 and SCOLOR 236. The two divided clocks, PCLK_M 224 and SCLK_N 226, as described, are output from Memory Control Unit 206 and passed back to DCG 204 as inputs to the phase detector 222.
FIG. 3 shows a timing diagram of signals associated with gear ratio Logic 228 with a 3/2 gear ratio. The cycle time of SCLK 210 is 3/2 times the cycle time of PCLK 208. PCOLOR 234 is incremented from a value 000 through a value 010 (i.e., 000, 001, 010) on each edge of PCLK 208. When PCOLOR 234 reaches a maximum value 010, PCOLOR 228 clears to 000 and in turn, toggles the value of PCLK/M 224. Thus, PCLK/M 224 alternates from 0 to 1 every three cycles of PCLK 208, or one cycle Tccyc 310.
On the other hand, SCOLOR 236 reaches a maximum value of 001 in this example, at which point the value of SCOLOR 236 clears to 000 and in turn, toggles the value of SCLK/N 226. Thus, SCLK/N 226 alternates from 0 to 1 every two cycles of SCLK 210, or one cycle TCCYC 310.
In a 3/2 configuration, PCOLOR 234 and SCOLOR 236 indicate the value of counts in progress for PCLK 208 and SCLK 210, respectively. PCOLOR 234 is asserted for three cycles of PCLK 208 (as shown by encircled 1, 2, and 3) and SCOLOR 236 is asserted for two cycles of SCLK 210 (as shown by encircled 1 and 2). Thus, PCLK/M 224 and SCLK/N 226 measure the relative phase of PCLK 208 and SCLK 210. Furthermore, as shown in FIG. 2, PCLK/M 224 and SCLK/N 226 are driven to a clock generator 220. Hence, SCLK 210 becomes a phase-aligned clock signal.
The value for PCOLOR 234 indicates when data read and write operations should take place to ensure data transfer at correct edges, referred to as color coding scheme.
However, the complex logics are introduced due to the phase align logics, gear logics and so on. This may make the implementation uneasy and inefficient. Additionally, if M and N are not co-prime numbers, the synchronizing edges of PCLK 208 and SLK 210 within the longer Tccyc 310 are wasted and the performance are thus degraded.
In view of this disadvantage, a new method and apparatus is disclosed to detect the synchronizing edges of the clocks in different domains which can be used to indicate when data read and write operations should take place in a digital system while having higher performance, speed and lower cost and also can be migrated into the new manufacturing process and conventional PLL easily.